Semiconductor chips are continually increasing in power, compactness and waste heat production. While they must be consequently cooled, for a number of reasons, this is generally not done by directly cooling the chip with a forced stream of cooling fluid or liquid. The surface area of the chip is small, and in order to contact that small surface with a sufficient and effective volume of coolant, the flow rate would be high, and chip surface might be eroded or damaged. Instead, as best seen in FIG. 2, computer chip makers typically protectively package semiconductor chips within a module, called a central processing unit or CPU. Chip 10, basically a layered silicon wafer, has a lower surface on which a so called ball grid array is disposed, sealed to a substrate 12 with a layer of sealant material 14. I/O connectors 16 extend through the substrate 12, and these are later connected to the circuit boards of a computer are other device by the manufacturer. Encapsulating the perimeter and upper surface of the chip 10 is a so called integrated heat sink 18 of conductive metal, typically copper or copper based alloy, which is formed around the chip 10 and bonded to the top surface by a conductive epoxy material layer 20. Epoxy 20 creates a permanent conductive bond to reduce thermal resistance, as well as providing a mechanical bond. The upper surface 22 of the heat sink 18 is highly polished and flattened, and generally protected with nickel plating. While the integrated heat sink upper surface 22 is larger than the surface of chip 10, even it alone does not provide sufficient conductive surface area.
As seen in FIG. 2, the end user of the CPU unit connects the I/O connectors 16 to a circuit board 23, and also bonds the upper surface 22 to the undersurface of a spreader plate 24 through a layer of compliant, thermally conductive “grease” 26. The upper surface of spreader plate 24 is covered with fins 28 or similar structures, across which a fluid is pumped to extract heat by forced convection. The overall structure of fins 28 and spreader plate 24 together are often referred to also as a heat sink. Here, however, to avoid confusion, just the spreader plate 24 and its particular thickness will be referred to in detail.
As seen in FIG. 3, the most significant portions of the CPU and the cooling mechanism may be schematically shown. Only the chip 10, epoxy layer 20, the upper thickness of the integrated heat sink 18 (that thickness located between the epoxy layer 20 and the upper surface 22), the thermal grease layer 26, and the spreader plate 24 are shown. Each layer in the three layer path, by virtue of its own inherent material properties, will have a pre determined thermal conductivity (conversely, resistivity), which, for a certain thickness of that material, will yield a certain thermal conductance (conversely, resistance). A layer twice as thick, all other things being equal, will have twice the thermal resistance, although its inherent resistivity does not change. While they are two sides of the same coin, the term thermal resistance will be used most often. The thermal grease layer 26 is almost negligibly thick, approximately 0.08 mm, but its thermal resistance (° F.-minute/BTU or ° C./Watt) is large, as compared to the metal layers above and below it, which have an inherently lower thermal resistivity and resultant lower thermal resistance. Together, the three thicknesses above the chip epoxy layer 20, in order, the upper layer of the integrated heat sink 18, the thermal grease layer 26, and the spreader plate 24, represent a three layer conductive path (conversely, resistive path) which the extracted heat must traverse. These are indicated at δ1, δ2 and δ3, for a total thickness δt Conventional wisdom makes the first thickness δ1 as small as possible to enhance the outflow of heat, since, for any given material, the conductive resistance will be directly proportional to its thickness. Typical δ1 thicknesses run from 1.0 to 1.5 mm, with 1.5 mm being depicted in FIG. 3. δ2, as mentioned, is very small, and dictated by considerations not typically within the control of the final assembler. δ3 will be dictated to a certain degree by heat spreading, manufacturing and weight considerations, being thick enough for robustness, but not so thick as to be overly heavy or expensive. Six mm is a typical thickness. The total conductive path thickness, will be somewhat limited by packaging considerations, as well. The total thermal resistance across the three layer path is, of course, the sum of the three resistances. So far as is known, no one has considered the three thicknesses as they relate to each other in a scientific way to determine what the best and most effective relative thickness proportions are, beyond the expressed desire to make δ1 as thin as possible. This “thinner is better” prejudice on the part of the CPU makers typically results in δ1 being significantly less than half of the total conductive path thickness, once the conventional δ2 and δ3 have been added, as indicated in FIG. 3.